1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a plurality of memory cells including capacitors. In particular, the present invention relates to a technology for automatically performing refresh operation to the memory cells.
2. Description of the Related Art
In general, dynamic random access memories (DRAMs) have been known as the semiconductor integrated circuit having memory cells including capacitors. The DRAMs are suited for higher integration since their memory cells can be made in smaller configuration. The DRAMs, however, require refresh operation in order to retain data stored in the memory cells. Semiconductor memories such as DRAMs need a precharge operation where bit lines are equalized after a read and a write operation. The read operation and the write operation cannot be performed during a precharging period so that the data input/output efficiency is lowered.
Therefore, in the recent DRAMs, a memory core is constructed of a plurality of memory banks independently operating. The input/output data efficiency is improved by allowing the operation of the other banks during the precharge period of a single bank.
Meanwhile, virtually SRAMs have been known as the semiconductor integrated circuit having both of the usability of static RAMs (SRAMs) and the high integration of DRAMs. The virtually SRAMs comprises controlling circuits for refresh operation and memory cores similar to those of DRAMs.
In the virtually SRAMs, a read cycle and a write cycle both include a time required for refresh operation so that the performance of the refresh operation does not show to the exterior. The virtually SRAMs are detailed in TOSHIBA REVIEW Vol.41, No.3, 1986, pp.227-230 (TOSHIBA KK).
In the virtually SRAMs, the cycle time required for read and write operations need to be longer than its actual time value by a time required for a refresh operation. This causes a problem of greatly extending access time.
There have not been proposed any DRAMs which operate at a cycle time equal to that of the conventional DRAMs and automatically performs the refresh operation. This is also true in the DRAMs having a plurality of banks.
It is an object of the present invention to provide a semiconductor memory which can perform refresh without being shown to exterior.
In particular, an object of the present invention is to perform refresh without being shown to exterior, in a semiconductor having a plurality of banks capable of independent operations.
According to one of the aspects of a semiconductor memory in the present invention, the semiconductor memory comprises a plurality of banks having memory cells and operating independently, a refresh circuit, a refresh counter, a holding circuit, and a refresh control circuit. The refresh circuit generates a refresh request for refreshing the memory cells at a predetermined interval. The refresh counter generates a refresh address. The holding circuit respectively holds information as to the completion/incompletion of refresh of the memory cells in each of the banks, the memory cells being designated by the refresh address. The refresh control circuit refreshes bank(s) yet to be refreshed among the banks not in operation upon the occurrence of the refresh request, based on the information held in the holding circuit. That is, under a single refresh address, banks yet to be refreshed are successively refreshed every time refresh request occurs. The refresh operations are performed on banks that are not in operation. Therefore, the refresh operations can be performed without being recognized from exterior. That is, the semiconductor memory having a plurality of banks can perform the refresh of memory cells internally and automatically.
According to another aspect of the semiconductor memory in the present invention, when all of the information held in the holding circuit indicates completion, the holding circuit changes all the information on completion to incompletion, and the refresh counter counts up. Therefore, the information corresponding to a single refresh address can be surely held to refresh the memory cells on the respective banks with reliability.
According to another aspect of the semiconductor memory in the present invention, the maximum time available for consecutive access to each of the banks is specified to be shorter than the interval at which the refresh request occurs. For example, even if a refresh request occurs simultaneously with the start of a read operation so that the refresh operation cannot be performed, the read operation will be completed by the time of the occurrence of the next refresh request. Therefore, the refresh operation is sure to be performed in response to the next refresh request. Accordingly, refresh cycles can be inserted to all the banks without fail, ensuring the refresh of all the memory cells.
According to another aspect of the semiconductor memory in the present invention, the semiconductor memory comprises a priority circuit. The priority circuit determines a bank to be refreshed when the banks not in operation include a plurality of banks yet to be refreshed. This makes it possible to perform the refresh of the banks without conflict.
According to another aspect of the semiconductor memory in the present invention, the semiconductor memory comprises a plurality of banks having memory cells and operating independently, a refresh circuit, an address generating circuit, a plurality of holding circuits, and a refresh control circuit. The refresh circuit generates a refresh request for refreshing the memory cells at a predetermined interval. The address generating circuit generates a plurality of refresh addresses. The holding circuits respectively hold information as to the completion/incompletion of refresh of the memory cells in each of the banks, the memory cells being designated by each of the refresh addresses. The refresh control circuit refreshes memory cells yet to be refreshed under the refresh addresses on the banks not in operation upon the occurrence of the refresh request, based on the information held in each of the holding circuits. That is, with respect to one of a plurality of refresh addresses, banks yet to be refreshed are successively refreshed every time refresh request occurs. The refresh operations are performed on banks that are not in operation. Therefore, the refresh operations can be performed without being recognized from exterior. That is, the semiconductor memory having a plurality of banks can perform the refresh of memory cells internally and automatically.
When a bank to be refreshed under a refresh address is in operation, another bank can be refreshed under a different refresh address. As a result, the maximum time available for consecutive access to each bank can be extended.
According to another aspect of the semiconductor memory in the present invention, the address generating circuit comprises a refresh counter and an address holding circuit. The refresh counter generates a refresh address. The address holding circuit holds the refresh address previously generated by the refresh counter. Therefore, a plurality of refresh addresses can be generated by a simple circuit.
According to another aspect of the semiconductor memory in the present invention, when all of the information held in one of the holding circuits corresponding to the address holding circuit indicates completion, one of the holding circuits corresponding to the refresh counter changes all of the information on completion to incompletion after transferring the held information to the holding circuit corresponding to the address holding circuit. The refresh counter counts up after transferring a current counter value to the address holding circuit. Therefore, even in the case where a plurality of refresh addresses are used to refresh the plurality of banks, the information held in the holding circuits can be kept associated with the refresh addresses for reliable refresh of the memory cells on each bank.
According to another aspect of the semiconductor memory in the present invention, the maximum time available for consecutive access to each of the banks is specified to be shorter than (interval at which refresh request occurs)xc3x97(number of banks)xc3x97(number of holding circuitsxe2x88x921). When a bank indicated of incompletion by a first holding circuit is in operation, a plurality of banks indicated of incompletion by a second and subsequent holding circuits (different refresh addresses) can be refreshed.
Specifying the above-mentioned maximum time to be shorter than a time obtained by multiplying the interval at which the refresh request occurs by xe2x80x9c(number of banks)xc3x97(number of second and subsequent holding circuits)xe2x80x9d ensures that any of the banks is refreshed upon each refresh request. That is, all the memory cells can be refreshed without fail even if the maximum time available for consecutive access to each bank is extended.
According to another aspect of the semiconductor memory in the present invention, the semiconductor memory comprises a priority circuit. The priority circuit determines a memory cell to be refreshed when the banks not in operation include a plurality of memory cells yet to be refreshed under the refresh addresses. Therefore, even if a plurality of refresh addresses are generated, the refreshes can be performed without conflict.